System Console
Table of contents
- 1. Quick-Start Guide
- 2. Documentation
- 3. TCL Macros
- 4. Preliminary Information
- 4.1.1.1.1. Java API
- 4.1.1.1.2. Beta Features
Welcome to the System Console page on Nios Wiki.
Altera's System Console is a TCL console that provides access to hardware modules instantiated in your FPGA. You can use the System Console for all of the following purposes:
- To create powerful verification instruments for your system
- To start, stop, or step a Nios II processor
- To read or write Avalon Memory-Mapped (Avalon-MM) slaves using special masters
- To sample the SOPC system clock as well as system reset signal
- To run JTAG loopback tests to analyze board noise problems
- To shift arbitrary instruction register and data register values to instantiated system level debug (SLD) nodes
System Console is intended as a low level tool for tasks such as board bring up and device driver debugging. System Console along with SOPC Builder provides the framework and baseline functionality that you need to compose your own sophisticated instrumentation and verification solution.
Quick-Start Guide
System Console presents a new and unfamiliar command set; hopefully, this SystemConsoleQuickStartGuide will help ease usage for starting users.
TCL Macros
While System Console provides the low level TCL commands, a lot of useful and powerful functionality can be derived from stringing a series of commands together. Since System Console is a full fledged TCL interpreter, these can be saved as TCL Macros in file, and then the file can be sourced in the shell and used.
Please share your TCL Macros here and extend System Console's capabilties.
- default_master - Simplified memory access commands for systems with only one memory master
bytestream console - Given a bytestream service, displays a simple console in a separate windows.- fill_memory - Various macros to fill a block of memory
- hexdump - Macro to display a hexdump of memory
- bsl430.tcl - Macro to program a Texas Instrument MSP430 micro-controller, using the BootStrapLoader (BSL) feature of the MSP430. Include Quartus/SOPC project, hardware schematic, TCL macro and sample files.
- find_service_by_name - Macro to locate a service path by the SOPC Component name. Must use -jdi option to start system-console.
- reset_system - Macro to reset system with the first found jtag_debug service path.
- Programmable Master - SOPC Builder test component which is controlled by system-console TCL scripts.
- Programmable Master NEEK DDR Analysis Example - This example contains many scripts that allow you to create stimulus to the NEEK DDR memory interface with the Programmable Master component.
- System Console Byte Stream Example - Using System Console to test and analyze streaming peripherals.
- Avalon Fast Downloader - An example component showing how to connect from jtag to Avalon MM, with drivers for system console. Allows downloads of 200-300KBytes/sec
Preliminary Information
The following posts are pre-release information. They are not guaranteed to be accurate, nor to remain accurate, in future releases.
Java API
Please use with the understanding that any API is subject to change.
- System Console 8.0 Java API - systemconsole-api-80.jar
- System Console 8.1 Java API - systemconsole-api-81.zip
- System Console 9.0 Java API - systemconsole-api-90.zip
- Tag page
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- What links here
Files 3
| File | Size | Date | Attached by | |||
|---|---|---|---|---|---|---|
 | systemconsole-api-80.jar No description | 923.55 kB | 04:54, 8 Dec 2008 | Admin | Actions | |
| systemconsole-api-81.zip System Console 8.1 Java API | 1933.38 kB | 00:38, 31 Jan 2009 | gkwan | Actions | |
| systemconsole-api-90.zip System Console 9.0 Java API | 3.5 MB | 22:14, 12 Mar 2009 | gkwan | Actions | |