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ResetAddress

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in sopc builder, more cpu setting, reset address
  this is the hardware reset entry point
a. if you set it to cfi flash, it will insert a altera supplied cfi boot loader by default, then load your program image to sdram, and jump to sdram.
b. if you set it to epcs, it will include a hidden onchip memory, with altera supplied epcs boot loader,
which will load your program image to sdram, and jump to sdram.
c. if you set it to onchip memory, then you need a custom boot loader on the onchip memory, which should load your program image to sdram. eg, you can store your image on IDE HDD, etc.

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I have a couple of questions regarding using this UART with uClinux that I am hoping someone will be able to answer: 1) Are any changes necessary to use it with the Altera Avalon UART drivers that are in the Nios II uClinux distribution? 2) If yes, are the interrupt routines coded in such a way that they will read or write all available characters from/to the FIFO's before returning from the interrupt? The Nios II has a very high IRQ overhead that I would like to minimize. Multimedia degree AND journalism degree AND Clinical Psychology Degree Online Web Development degree AND Online Educational Psychology Degree
Posted 11:21, 1 Mar 2010
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