FlashProgrammer

During development, we use nios2-configure-sof and nios2-download to config the FPGA and run Nios II program from SDRAM. But the content of FPGA and SDRAM will lose when power off. To enable the system to start from power on, we need to write sof and program to flash. But flash have limited write life and the write speed is slow, so you should not program the flash until you have your system mostly tested.

Though we can use JTAG UART as console with nios2-terminal during development. You should not use it as console device if you want your system to start automatically when power on. Because the JTAG UART will hang without a nios2-terminal connected. You should use Serial UART with a RS232C cable instead. You can keep both the JTAG UART and serial UART in SOPC builder, but you must disable "Support for console on Altera JTAG UART" in kernel config and rebuild the kernel image. Please check LinuxConfig about how to select the other console device instead of JTAG UART. You have to test the new kernel image with nios2-download. Don't run nios2-terminal, use minicom on Linux or Hyper-terminal on Windows. Make sure it runs correctly over the RS-232C COM port.

Only after you have tested the program from sdram, you may try to write the flash. You will write the sof and program image seperately. You must find out what kind of flash you will use. There may be CFI flash, or EPCS flash, or both of them. 

First, you must decide where to configure FPGA, from CFI or EPCS. This will mostly depend on the hardware, config mode pins or CPLD. You need to check the manual if it is a dev board. For DE2, DE1, some eval and starter boards, the sof is loaded in EPCS flash. For most other Altera dev boards, you can select one either CFI or EPCS with the CPLD. The CPLD will control the config offset on CFI, eg, 0xc00000.

Next, you must decide where to store the program. Most dev boards have a CFI flash, and you can use it by default. If your board have space on EPCS, you may use it but EPCS is usually slower than CFI during read. You must tell which component to use for reset vector, CFI flash or EPCS controller, in SOPC builder. If you change it, you regenerate the sof. You don't need to rebuild the kernel image.

The Altera flash conversion utility can add a Altera supplied boot loader, which will load the image to SDRAM and execute. The kernel image is compiled to start from SDRAM, (sdram base + boot link offset of the uncompress loader). So the start up procedures will be

1. power on reset
2. config sof from flash to FPGA
3. Nios II CPU start at the reset vector, which contain the boot loader
4. the boot loader copy program image from flash to SDRAM, at (sdram base + boot link offset) for our zImage
5. the uncompress loader in our zImage, copy the real kernel image to (sdram base)
6. kernel start up

Check your kernel dir, linux-2.6.x/include/nios2_system.h or check in SOPC builder , to find out the EPCS controller, or CFI flash 's base address. You will need these address value for flash programming.

You may find the boot loader sources at your altera suite installation,
/opt/altera9.0/nios2eds/components/altera_nios2/boot_loader_sources

So we might have at least four alternatives,
1. sof in EPCS, program in CFI (default for DE2, DE1, some eval and starter boards)
2. sof in CFI, program in CFI
3. sof in EPCS, program in EPCS
4. sof in CFI, program in EPCS   ( in very rare case)