EPCSGuide

1. The Devices
2. Applications
1. 2.1. Configuring the FPGA
2. 2.2. Booting an application
  1. 2.2.1. Booting uClinux

The EPCS series of configuration devices provided by Altera can be used for much more than just configuring the FPGA. Given their relatively high cost, it would only make sense to use these devices to their fullest extent. This guide will address what you can do with remaining space on an on-board EPCS device, with a specific focus on uClinux applications. The three primary applications of interest will be configuring the FPGA, booting application code or a kernel, and finally, creating and mounting read/write filesystems.

The Devices

The EPCS devices currently come in 4 flavors; EPCS1, EPCS4, EPCS16 and EPCS64. These translate to 1,4,16 and 64 MBit Flash devices respectively. Basically, they are just re-branded SPI Flash devices with minor changes in Silicon ID Codes (to prevent the user from replacing an EPCS device with a cheaper SPI device). Typically, the EPCS16 and 64 devices are needed to do anything useful beyond configuring the FPGA itself.

Since they are essentially SPI Flash devices, their physical interface simply consists of the signal set: MISO, MOSI, SSn and CLK. To use these devices, Alteras EPCS Controller must be used; this controller is essentially an SPI Controller, with the first 256 words being ‘boot-rom’. The actual registers themselves, and their functionality, are defined in Alteras SPI Controller Manual. The EPCS controller manual does not address functionality of the registers, as they are ‘protected’.

Applications

This section will address the various applications of EPCS configuration devices. These applications may be combined in any order (use of all is recommended!). As a note, most of the applications involve use of the NIOS SDK Shell (not the IDE), so now is a good time to become familiar with it if you aren’t already.

Configuring the FPGA

The primary purpose of the EPCS device is to configure the FPGA with SRAM configuration data. This translates to downloading the ‘hardware’ image onto the FPGA on powerup. When the FPGA is powered up, the MSEL pins determine how the FPGA is configured (refer to the appropriate FPGA datasheet for more info). IF the MSEL pins indicate a configuration attempt via an EPCS Device, the EPCS device will load the appropriate hardware image if present. This is the goal of this task; to load the EPCS device with configuration data.

Configuration data is specified in the form of an SOF file that is typically downloaded to the FPGA while developing, using the Quartus programmer. Once a design is in a stable state to be loaded upon powerup, the following should be done inside the SDK Shell:

· sof2flash --input=<SOF File> --output=<SOF SREC File> --epcs –-verbose –-offset=0x0

o This step converts the SOF File to an SREC file which can be programmed to the EPCS Device.

o Note: An SREC file is simply a text file that specifies binary data and where it should be loaded. 0x0 is the first address of the EPCS Device.

·Now that an SREC file is generated, it can be downloaded to the EPCS device. In order to do this, you must find the base address of the EPCS Component using SOPC Builder. Then, use the following command to download the SREC file:

o nios2-flash-programmer –debug –-base=<base addr in hex> --epcs <srec file>

o Note: When this is invoked, it should also tell you where the actual registers for the EPCS component were found. As mentioned before, the base address for the SOPC component IS NOT the base address for the registers, because there are 256 words of boot-rom. The base address for the registers (register base) is where the SPI Controller registers reside. This number should be recorded for later use.

o Power cycle your board, and check to see if it was programmed successfully.

Booting an application

If a NIOS Processor is present in your design, it would be desirable to boot application code upon powerup as well. Altera provides bootloading code that simplify the boot process. The following process can be used to boot simple application code, or boot something as complicated as a uClinux kernel, as will be described shortly.

·Whenever an application is built, whether in the NIOS IDE or using the uClinux toolchain, an ELF binary is generated that can be directly downloaded to RAM. This is typically done using:

o nios2-download –g <elf file>; nios2-terminal

·This process will convert that ELF file to another SREC file. The difference here is that this SREC file will contain, in the header, boot-copying code to instruct the NIOS processor to copy the contents of the EPCS device to RAM, and then execute. This effectively copies your ELF file from the EPCS device to RAM, and then executes it as if you were downloading directly to RAM. Note: It is important that you specify the reset address of the NIOS Processor, in the SOPC Builder, to be the EPCS Device. Otherwise, your processor will not execute code from the EPCS Chip.

· To convert the ELF File to a downloadable SREC file, with a boot-copier, execute:

o elf2flash –-input=<elf executable> --output=<ELF SREC File> --location=<offset into EPCS Device> --epcs –-boot=<path to boot copier>

·If you wish to configure the FPGA as well, insert the line:

o -–after <sof SREC file>

o Remove the –-location tag

o This positions the ELF SREC file after the configuration data so they can both co-exist on the same device.

o The boot copier for EPCS is typically located in <$SOPC_KIT_NIOS2>/components/altera_nios2/boot_loader_epcs.srec

·Download to the EPCS Device using:

o nios2-flash-programmer -–epcs -–debug -–base=<base addr> <ELF SREC File>

·Power-cycle your board and start the NIOS2 terminal; the application should now boot.

Booting uClinux

The previous method can be used to boot uClinux as well; the generated kernel is simply an ELF executable that can be downloaded in a similar fashion. It is recommended that a compressed kernel be generated by usingmake zImage. Note the location of the zImage file, and then execute the previous commands using the path to the zImage file as the ELF binary. Power-cycle the board, and it should configure the FPGA as well as boot the compressed kernel automatically!

It is highly recommended that an Initramfs filesystem be compiled in with the kernel. Refer to the uClinux guide for this, as it will not be discussed in this document. By using an initramfs filesystem, a kernel along with a root filesystem can be booted directly from the EPCS device (and then RAM), allowing for quicker access times.

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