This tutorial teaches you how to use SOPC Builder, the Quartus II software, and the
Nios II Embedded Design Suite to implement a digital picture viewer in a
Cyclone III FPGA. In this tutorial, you build a processor-based hardware system in
programmable logic for the Nios II Embedded Evaluation Kit, Cyclone® III Edition
(NEEK) and run software on it. The tutorial demonstrates the steps to build complete,
complex embedded designs using the Altera design software.
Downloads:
Lab Manual (PDF)
Design Files (ZIP) for Quartus II and Nios II EDS v9.0
Target Hardware: Nios II Embedded Evaluation Kit
High Level Block Diagram of the Digital Picture Viewer