Page last modified 17:55, 2 Apr 2010 by Joe D?
Nios Community Wiki > ExampleDesigns
ExampleDesigns
Table of contents
- 1. Starter Designs
- 2. DevBoard Design Updates
- 3. Ethernet/Networking
- 4. File Systems
- 5. Memory
- 6. Boot Loading
- 7. Multimedia
- 8. Misc.
Welcome to the Nios II Example Designs page. Feel free to post your example designs.
Starter Designs
- HelloLED - This is an example of a "freestanding" application, one that realizes a minimal footprint. Freestanding programs "own" the hardware and are responsible for initializing all hardware devices, device-drivers, and system-services.
- Cyclone III - Nios II - Starter board - How to get Nios II running from scratch on the Cyclone III starter kit.
- NiosII 3C120 Design Example - This is a hardware design example for the Altera 3C120 development board.
DevBoard Design Updates
- StratixIII 3sl150 dev niosII standard update- Fixes an error in the flash connectivity at the top level.
Ethernet/Networking
- Small TSE MAC Ethernet Example - This design uses the Altera Triple Speed Ethernet Megacore configured as the Small MAC variation to achieve lower FPGA resource usage. It was created using version 7.2 of the Altera tools and targets the Nios II Development Board, Cyclone II Edition.
- Simple Socket Server Plus - This example is an enhanced version of the Simple Socket Server (SSS) example that Altera has shipped for the past few years. The primary enhancements to this example are, enabled the InterNiche FTP server, enabled the InterNiche TFTP server, enabled the InterNiche FTP Client, enabled the InterNiche TFTP Client, enabled the InterNiche Telnet server, enabled the InterNiche console, enabled the InterNiche VFS file system, enabled the Altera ROZIPFS file system.
- Superloop Simple Socket Server Plus - This is a SUPERLOOP implementation of the Simple Socket Server Plus application. In this example the application is compiled with the InterNiche Stack running in superloop mode, without an RTOS.
- Web Server with AJAX Progress Bar - This extends the webserver that is shipped with the Nios II EDS to support a simple AJAX-based progress bar during upload in addition to performance and memory footprint improvements. Any/all feedback welcome!
- Nios II UDP Offload Example - This example demonstrates a method of offloading UDP packet traffic from a Nios II system such that it can be processed in hardware rather than in software.
File Systems
- ReadOnlyZipFileSystem - This is a simple example of how to use Altera's read-only zip filing system.
- HostFileSystem - This is a simple example of how to use Altera's GDB Host file system.
Memory
- Numonyx M18 SCSP StrataFlash with PSRAM interface ( AD-Mux) - This peripheral was created to dirve the Numoyx M18 AD-Mux dual die FLASH/PSRAM parts. It muxes address and data on the same bus and can share the tri-state birdge with other peripherals.
- Off-chip memory PLL tuning example - Demonstrates how to find the optimal clock phase offset for your off-chip memory(ies).
Boot Loading
- BootLoaderFlashExample- This example shows how one might create an intelligent flash based boot loader that can analyze multiple possible application images stored in flash memory and choose the latest revision that is valid in the flash, load it into system memory, and jump to it.
- AlternateNiosBootMethods - This is an example of how to implement your own custom boot copier software using the Nios II processor and Nios II IDE. Additionally, you will understand the basics of how to externally control the Nios II boot process.
Multimedia
- NEEK "video" design example - This is the design example that was released on the 8.0.1 NEEK CD called "video". The design has been ported into the Altera 9.0sp1 tools and posted as this example.
Misc.
- InterfacingToThePPC- This is an example of how to interface the PPC8439e to the avalon bus. These examples are not necissarily functional since they were never tested in hardware but are intended as an essay writing help to someone who might be writing their own.
- HighSpeedImageDownloadDemo- This example contains a simple system build on a 1C20 Nios dev board with a Lancelot VGA board. It shows how one might create a high speed download application from a host PC to a Nios II target system via the JTAG UART. This example can demonstrate data transfers between 0.5Mbps and 1.0Mbps consistently between the host and target over the JTAG UART. This download contains the entire source for the hardware and software in this example resume.
- Nios II Embedded Processor Design Contest - Outstanding Designs - Winning entries from the Nios II Embedded Processor Design Contest
- C2H Mandelbrot Legacy Design - This example demonstrates using C2H to accelerate a processor intensive algorithm in dedicated hardware.
- ExampleDesigns/NiosII3C120DesignExample
- FIFOed Avalon Uart - This peripheral is a supper set of the Altera Avalon UART. The most important new feature is addition of Rx and TX FIFOs which are configurable in size and IRQ properties.
- SOPCSystemResetConsiderations - discusses issues that should be considered when implementing SOPC Builder systems which contain PLLs embedded in the components or instantiated inside or outside of the system.
- Nios II Command Line Example - This Intelligent Command Line design example for Nios IIprovides a way that designers can execute different commands to issue different operations in the shell.
- Avalon MicroSequencer Example - This example shows how to use a microcoded sequencer to access memory mapped periperals.
- Avalon State Sequencer Example - This example shows how to use a state sequencer to access memory mapped peripherals.
- SGDMA Example - This simple design moves data from one memory location to another using a pair of scatter-gather DMAs.
- DDR Memory Half-Rate Bridge Example - This design includes a half-rate bridge between the Nios II processor and DDR SDRAM memory.
- Modular SGDMA Video Frame Display Example - This design includes the modular SGDMA which is used to display frames on a 800x480 LCD display.
- Avalon ST Computational Pipelines - discusses how to create high performance and very flexible computational pipelines in the Avalon ST environment within SOPC Builder.
- Nios® II Hardware Mailbox with Interrupts - A faster ,smaller, single clocked mailbox component. Altera Avalon Mailbox
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